The present invention generally relates to a metric for automatic defect classification in semiconductor wafers. More specifically, for a predetermined stage in a semiconductor fabrication process, the present invention relates to a method for automatic defect classification in a die or integrated circuit of semiconductor wafers for estimating the effect of defects on functionality. Furthermore, the present invention""s method of classification gives rise to new possible classes, based on the actual damage caused by a specific defect.
Numerous methods are known and described in the literature of semiconductor fabrication process testing and quality assurance. Essentially these processes define the calculation of statistical metrics which vaguely correspond to theoretical intersections between, on the one hand, an area measure for defects and the like and, on the other hand, an area measure for the intentionally printed conductive pattern found on a predetermined region of a semiconductor wafer.
There is a need in the art for an improved method of testing and assurance, be it an improved statistical method, or an improved deterministic method, or an improved combination thereof. It should be recalled that another critical aspect of semiconductor testing and assurance relates to the amount of time consumed by such a method. In terms of an in process testing and assurance method, speed is of the essence. Therefore, a reduction of delays in process testing would likewise represent a significant improvement to the art. Furthermore, an improved testing and assurance method that will facilitate reprocessing of defective batches of wafers would also constitute an improvement to the prior art.
There is a further need in the art to classify defects on semiconductor wafer layers or dies in terms of the relationship between the defects and the surrounding conductive patterns, and to classify defects in terms of their effect on production yield. Additionally, there is a need in the art for the classification of defects relating to missing conductive patterns or portions thereof.
The present invention will be described with the requisite particularity based on preferred embodiments. However, those versed in the art will readily appreciate that various modifications and alterations may be carried out without departing from either the spirit or scope, as hereinafter claimed.
In describing the present invention, explanations are presented in light of currently accepted scientific Technological or Process Control theories and models. Such theories and models are subject to changes, both adiabatic and radical. Often these changes occur because representations for fundamental component elements are developed, because new transformations between these elements are conceived, or because new interpretations arise for these elements or for their transformations. Therefore, it is important to note that the present invention relates to specific technological actualization in embodiments. Accordingly, theory or model dependent explanations herein, related to these embodiments, are presented for the purpose of teaching ordinarily skilled artisans how these embodiments may be substantially realized in practice. Alternative or equivalent explanations for these embodiments may neither deny nor alter their realization.
In addition, the following definitions will be useful for understand the invention as described herein:
Kill Index: Generally, the kill index is a descriptor carrying information regarding the estimated kill rate of a defect. A xe2x80x9ckill ratexe2x80x9d implies a rate, which is an average (i.e. statistical entity)xe2x80x94and statistical decision making is often employed using a kill rate in order to determine the fate of a batch according to an examination and classification of a few constituent members of that batch. Nevertheless, the xe2x80x9cKill Indexxe2x80x9d, per se, is not a statistical measure. It is a deterministic metric, derived from the topological relationship between the defect and surrounding imprinted pattern objects, that is related to the damage caused by this defect to the specific integrated circuit. xe2x80x9cKillxe2x80x9d is used to denote a dysfunctional integrated circuit.
Killer Defect: A defect, which renders a single die (which corresponds to a single integrated circuit) or portions thereof unable to function adequately or reliably.
Pattern blobs: Distinct pattern areas in a wafer layer or die, defined by a continuous border separating them from the background; for example conductive pattern portions in a wafer layer.
Reference Image: A magnified segment of a layer or die of a semiconductor wafer having no defects either relating to faults in the predetermined topology of the pattern or to additional particles.
Defect Image: A magnified segment of a layer or die of a semiconductor wafer having defects either relating to faults in the predetermined topology of the pattern or to additional particles.
Reference Map: A predetermined image mask of the required pattern topology of each layer of a semiconductor wafer.
Reference Rule Set: A protocol relating to definitions of the geometric shapes and sizes of elements of the topology of a layer or die of a semiconductor wafer such as a straight edge, a specific curvature, intersecting angles and specific lengths.
Non-predetermined Portion: Defects in a semiconductor wafer or layer thereof, random with respect to position even if systematic with respect to process.
Also, the following acronyms are referred to in the following description:
ADC: Automatic defect classification.
CDM: Chamfer distance map.
DFP: Defect""s footprint.
EDS: Electron dispersion spectroscopy.
FOV: Field of view.
IPDM: Integer pattern dilated map.
ND: Number of dilations.
PBM: Pattern binary map.
PCZSM: Pattern Complement Zoomed Segment Map (ZSM).
RCFR: Reference to class FOV ratio.
SEM: Scanning Electron Microscopy.
ZSM: Zoomed Segment Map.
In the process of manufacturing semiconductor wafers, quality control and assurance testing of all parameters is needed after each processing step. An important aspect of this testing relates to classification and detection of the presence and location of defects resulting from the previous manufacturing step. Furthermore, it is necessary to determine if such defects will render the currently exposed layer, die or integrated circuit of the wafer, or presumptively a batch of wafers, incapable of functioning adequately and reliably. Defects that result in a batch of wafers being unsatisfactory are termed xe2x80x9ckiller defectsxe2x80x9d. This stage-wise testing and defect classification procedure relates to the exposed layer portion of each wafer subsequent to each manufacturing step.
The present invention relates to embodiments of a kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. This method includes the steps of
a) locating a region having at least one non-predetermined portion therein;
b) determining a predetermined topology for the region;
c) calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region; and
d) assigning a kill index classification using the calculated evaluation parameters.
More specifically, the kill index that is assigned is linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.
Simply stated, the method relates to an analysis of the geometrical relationship between a non-predetermined portion, generally referred to as defects, and the surrounding predetermined topology of the conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of the currently exposed layer, die or integrated circuit of the wafer. Further, in accordance with this geometrical information, a classification of the effects of defects into a numerical value, the xe2x80x9ckill indexxe2x80x9d, is achieved.
According to an embodiment of the present invention, the kill index classification method in which the step of locating a region having at least one non-predetermined portion therein includes the steps of
a) accepting at least one appropriate resolution image of the region and
b) using the at least one appropriate resolution image analyzing the region to determine if there is a rule violating shaped portion located therein.
According to a variation of an embodiment of the present invention, the kill index classification method in which the step of accepting at least one appropriate resolution image of the region includes the steps of accepting a reference image, and accepting a defect image. Furthermore, the step of analyzing the region to determine if there is a rule violating shaped portion located therein includes the step of comparing the reference image with the defect image.
According to another variation of an embodiment of the present invention, the kill index classification method in which the step of accepting at least one appropriate resolution image of the region includes the steps of accepting a reference map, and of accepting a defect image. Additionally, the step of analyzing the region to determine if there is a rule violating shaped portion located therein includes the step of comparing the reference map with the defect image.
According to an additional variation of an embodiment of the present invention, the kill index classification method in which the step of accepting at least one appropriate resolution image of the region includes the steps of accepting a reference rule set, and of accepting a defect image. Furthermore, the step of analyzing the region to determine if there is a rule violating shaped portion located therein includes the step of comparing the reference rule set with the defect image.
According to a variant of an additional variation of the abovementioned embodiment of the present invention, the kill index classification method in which the step of accepting a reference rule set includes a threshold for at least one topological feature selected from the list of a detected edge discontinuity, a detected edge curvature, an interior angle formed from two intersecting detected edges, an exterior angle formed from two intersecting detected edges, a fabrication mask topology design principle, or the like.
Simply stated, in the application of this embodiment of the present invention, a set of rules or standards, generally geometric in nature, replaces or supplements the use of a defect-free reference image on a reference map segment to determine the existence of defects. This technique facilitates detection of defects relating to pattern deformation, additional patterns and absence of pattern portions as well as detection of defects such as unwanted particles.
According to another embodiment of the present invention, the kill index classification method, having the step of determining a predetermined topology for the region, includes at least one step selected from the list of examining a reference image, examining a reference map, or examining a fabrication mask topology design algorithm methodology used to produce the reference map.
According to an additional embodiment of the present invention, the kill index classification method in which the step of calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region includes the step of assigning a topology intersection parameter for the juxtaposition of the at least one non-predetermined portion with the predetermined topology.
According to a further embodiment of the present invention, the kill index classification method in which the step of assigning a kill index classification using the calculated evaluation parameters includes convoluting the calculated evaluation parameters into a numeric classification.
Furthermore, according to an embodiment of the present invention, the kill index classification method in which the step of assigning a kill index classification using the calculated evaluation parameters includes convoluting the calculated evaluation parameters into a multi-parametric classification coordinate.
Simply stated, a kill index relating to the relative positions of defects and pattern is specified substantially as a numerical value or as a chart of these factors or as a three-dimensional metric, as a multi-parametric function or the like.
According to another embodiment of the present invention, the kill index classification method in which the step of locating a region having at least one non-predetermined portion therein includes locating a region having at least one defect footprint. According to a variation of an embodiment of the present invention, the kill index classification method in which locating a region having at least one defect footprint includes locating a region having at least one multi-component footprint. This implies that a defect footprint includes the presence of multiple defects and not simply the largest or most significant defect.
Moreover, according to yet a further embodiment of the present invention, the kill index classification method in which the step of calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region includes the at least one non-predetermined portion having at least one non-predetermined portion core class of at least one pattern non-predetermined portion selected from the group comprising an extra pattern connected, an extra pattern isolated, a missing pattern, a deformed pattern and the like. Alternatively, at least one particle non-predetermined portion includes an element selected from the group comprising a crater in the pattern, a crater in the background, a particle on the pattern, a particle on the background, a particle on distortion, an embedded under pattern, or an embedded under background.
According to a further embodiment of the present invention, the kill index classification method in which the step of calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region the evaluation parameters include at least one parameter selected from the list:
a) a non-predetermined portion isolated from the predetermined topology;
b) a non-predetermined portion close to the predetermined topology;
c) a non-predetermined portion connected to the predetermined topology;
d) a non-predetermined portion bridging the predetermined topology; and
e) a non-predetermined portion close to bridging the predetermined topology.
More specifically, the relative distance between a defect particle and an adjacent pattern is relevant to whether the defect will adversely affect the functionality of a wafer. Generally, defect particles at a sufficiently large distance from the pattern, will not interfere with functionality. Similarly, a particle close to or connected to a single pattern portion or blob is unlikely to cause a problem. Clearly, a particle causing a short across two or more pattern blobs by bridging is problematic, and such a defect is classified as a xe2x80x9ckiller defectxe2x80x9d. Where a defect particle is defined as close to bridging, whether this will be termed a killer defect, depends on whether the closeness is of the order of a single pixel in the defect map, making distinguishing between touching and close problematic.
According to a variation of the abovementioned embodiment of the present invention, the non-predetermined portion isolated from the predetermined topology includes a distance greater than a predetermined distance between the at least one non-predetermined portion and a pattern portion of the predetermined topology.
According to another variation of the aforementioned embodiment of the present invention, the non-predetermined portion close to the predetermined topology includes a distance less than a predetermined distance between the at least one non-predetermined portion and a pattern portion of the predetermined topology.
According to an additional variation of the aforementioned embodiment of the present invention, the non-predetermined portion connected to the predetermined topology includes the at least one non-predetermined portion being in contact with a pattern portion of the predetermined topology.
According to a further variation of the aforementioned embodiment of the present invention, the non-predetermined portion bridging the predetermined topology includes at least one parameter selected from the list:
a) at least one non-predetermined portion connecting at least two pattern portions of the predetermined topology;
b) at least one non-predetermined portion connecting at least one pattern portion and intersecting at least one other pattern portion of the predetermined topology; and
c) at least one non-predetermined portion intersecting at least two pattern portions of the predetermined topology.
According to another variation of an embodiment of the present invention, the non-predetermined portion close to bridging the predetermined topology includes the at least one non-predetermined portion being close to at least two pattern portions of the predetermined topology.
Generally there are two basic embodiment families of the present invention, which relate to assigning a kill index classification for any imaged region of the exposed layer of an in-process wafer. One of these families relates to the exposed layer as a two-dimensional image while the other uses relative height information for each pixel or pixel-cluster in the image to provide a more refined kill index classification. Each of these basic embodiment families can be adapted for use in the context of any explicitly described embodiments, variants, and so on.
It should be recalled that the killer index classification of the present invention is preferably used in conjunction with a system for specifying the material properties (conductive, capacitive, resistive, non-conductive and so on) of each mapped pixel or pixel-cluster in a critical process control decision such as disqualifying the currently exposed layer, die or integrated circuit of the wafer or wafer batch or directing a wafer batch to a corrective step such as pattern stripping or reworking.